1. Field of Invention
The present invention relates to a semiconductor device and to a method of manufacturing a semiconductor device and more specifically to a MOSFET for controlling short-channel effects.
2. Description of Related Prior Art
As miniaturization of semiconductor IC's advance, controlling short channel effects of MOS transistors is critical in terms of guaranteeing values for cutoff properties and threshold voltage.
The short-channel effect is the phenomena observed in the shorter gate for MOS transistors as a result of miniaturization, in which the lateral widening of the depletion region of a drain diffusion layer comes close to the depletion region of the source diffusion layer, causing punchthrough or bipolar behavior. This causes current leakage and makes it impossible for the gate voltage to control current flow, which lowers the threshold voltage.
Therefore, suppressing the depletion region of the conductive source/drain diffusion layer and specifically decreasing the depletion region is effective in suppressing short-channel effects. A MOS transistor of conventional technology is illustrated in FIG. 6, in which the lateral width of the depletion region 29 is controlled to decrease short-channel effects.
A heavily doped p+ region 11 is formed deep in the depletion region 29. When the p+ region 11 has the same height as the diffusion layer 12, this is a situation which makes the lateral widening of the depletion region difficult.
The structure illustrated in FIG. 6 is formed by a mask aligning technique using the ion implantation method. As is clear in FIG. 6, ions are implanted wider than required, which takes the depletion region into account. A heavily doped region is also formed under the drain layer, generating junction capacity between the diffusion layer (source/drain layer) and the heavily doped region. This junction capacity impedes an increase in the device operation speed.
A technology designed to decrease the junction capacity between a heavily doped region and a diffusion layer is disclosed in Japanese patent Kokai H7-183392. This technology is briefly described herein in connection with FIG. 7(a-c). As illustrated in FIG. 7(a), a device isolation dielectric layer 2 is formed by a normal LOCOS method on a p-type semiconductor substrate 1 to provide a gate dielectric layer 3 by a thermal oxidation method. Then, by an ion implantation method, a p-type heavily doped region 4 is formed having a higher dopant concentration than that of the semiconductor substrate 1. After that; gate electrodes 5 are formed at predetermined locations.
Next, as illustrated in FIG. 7(b), elements such as Si and Ar are implanted, using the gate electrodes 5 as masks, to purposely form point defects, e.g. voids of interstitial Si, on the surface of a semiconductor substrate 1 except directly below the gate electrodes 5. Immediately after this, these point defects are annealed by oxidation ambiance. Consequently, the point defects are diffused at an accelerated rate to lower the concentration peak in the heavily doped region while the point defects amass on the surface of the semiconductor substrate, leaving a p-type heavily doped region 4 only directly under the gate electrodes 5.
Then, using the gate electrode as a mask, a dopant is introduced to form a diffusion layer 6 which is used as a source/drain (FIG. 7(c)).
The AB cross section of FIG. 7(c) is profiled in FIG. 8. In FIG. 8, the y-axis shows dopant concentrations while the x-axis shows position location from point A to point B.
As is apparent in the method described above, the concentration peak is lowered by introducing point defects on the surface of a semiconductor substrate 1 and by annealing it to accelerate the diffusion of the dopant in the heavily concentrated region except directly under the gate electrode 5 (FIG. 7(c)). That is, the part of the dopant in the heavily doped region 4, except the part directly under the gate electrode 5, has a lower but still noticeable concentration of dopant. FIG. 8 shows this status.
Therefore, it is possible to reduce the junction capacity between the diffusion layer 6 and the heavily doped region 4, while still retaining the junction capacity.
The present invention intends to resolve the above mentioned problems and to provide a MOSFET structure which is substantially immune to short-channel effects and thereby permitting an increase in the operational speed of the semiconductor device.
It is accordingly an object of this invention to provide a semiconductor device comprising diffusion layers of the inverse conductivity type formed at a predetermined distance on the surface of one conductivity type semiconductor substrate. A gate electrode is formed between the diffusion layers. A heavily doped region of the same conductivity type as the semiconductor substrate is formed under the gate electrode such that it does not contact the diffusion layer (source/drain). The dopant concentration drops significantly at the junction between the heavily doped region and the semiconductor substrate relative to the dopant concentration in the heavily doped region.